1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to an integrated bus bridge and memory controller that enables data streaming to a shared memory resource while maintaining cache coherency.
2. Background
Prior computer systems commonly include a main processor or host processor that communicates with other elements of the computer system via a processor or host bus. Other elements coupled to such a processor or host bus typically include one or more cache memories as well as a main memory for the computer system. Such a main memory is typically comprised of dynamic random access memories (DRAM).
Prior computer systems may also include one or more peripheral buses that enable communication among a variety of peripheral components. Such a computer system may also include bridge circuits that enable communication between the processor or host bus and the peripheral buses. Such a bridge circuit typically enables communication between the main or host processor and the various bus agents coupled to the peripheral bus.
In addition, the bus agents coupled to such a peripheral bus may require access to the main memory of the computer system. In such a system, the data stored in the main memory may be modified either by the main processor or host processor or other elements coupled to the processor bus as well as various bus agents coupled to the peripheral buses.
In some prior computer systems, such peripheral buses usually enable extremely high speed or high bandwidth communication. For example, the peripheral component interconnect (PCI) published bus specification allows data communication bandwidth of up to 133 megabytes per second. Unfortunately, prior computer systems typically limit the available bandwidth on such a peripheral bus well below the maximum allowable provided by the published standard.
Typically, the bandwidth on such a peripheral bus is limited by the cache coherency transactions that occur on the host or processor bus during memory access transactions that initiate from the peripheral bus. For example, one prior computer system employs an integrated bridge and memory controller circuit that functions as a bus bridge between the host or processor bus and a peripheral bus while at the same time functioning as a memory controller for the main memory of the computer system. Such a system typically limits each atomic data transfer transaction on the peripheral bus targeted for the main memory to a single data line or cache line.
For example, in such a system, during a memory write transaction that originates on the peripheral bus, a prior integrated bridge and memory controller usually receives a data line over the peripheral bus and generates a corresponding snoop request over the processor bus. After the appropriate line invalidate or write back transaction on the host or processor bus, the integrated bridge and memory controller then transfers the data line to the main memory. Unfortunately, such a bridge and memory controller usually cannot immediately accept a subsequent line of data over the peripheral bus during a data streaming transaction. Instead, such an integrated bridge and memory controller usually signals an end to the write transaction on the peripheral bus. Thereafter, the initiating bus agent on the peripheral bus typically initiates another write transaction to transfer the next data line to the main memory.
Such a system that limits atomic transfers to a single data line ensures that the integrated bridge and memory controller obtains a data line address from the originating bus agent on the peripheral bus for each data line transfer to the main memory. The integrated bridge and memory controller typically uses the address for each data line to initiate a snoop request over the processor or host bus. A memory controller could generate addresses for each data line transferred over the peripheral bus in order to provide the proper snoop request transactions on the processor bus. However, such address generation logic typically increases the complexity and cost of such a memory controller and drives up the overall system cost.